1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device including electrically rewritable memory cells.
2. Description of the Related Art
As one of electrically rewritable nonvolatile semiconductor memories (electrically erasable programmable read-only memories (EEPROMs)), a NAND type flash memory is known. Since the NAND type flash memory is nonvolatile and can realize a capacity enlargement and dense integration, the usage thereof is expanding.
Along with the trend of the NAND type flash memory toward a capacity enlargement, the number of memory cells connected to bit lines increases. Then, it is necessary to extend the bit-line length, and leads to an increase in each of the capacity of the bit lines and the resistance thereof. In addition, since space between bit lines gets narrowed in accordance with reduction in a chip size, the capacitive coupling between bit lines is intensified.
The NAND type flash memory controls the bit lines upon data writing as, for example, described below. Unselected bit lines to which non-writing memory cells are connected are charged to have a power supply voltage VDD (for example, 2 V), while selected bit lines to which memory cells to be written are connected are discharged to have a ground voltage VSS (0 V).
Under such control, when the bit-line length is large, since the bit lines have a high resistance and a high capacity, it takes much time to charge or discharge the bit lines. Therefore, the operating speed of the NAND type flash memory decreases.
As a related art, the technology for speeding up read and verification operations by dividing the bit lines into groups has been disclosed.